`timescale 1ns / 1ns

module mult_array2 (
	input  wire         clk,
	input  wire         rst_n,
	input  wire [1023:0] data1,      // 32个32位有符号数
	input  wire [255:0] data2,       // 32个8位有符号数
	output wire [1279:0] result      // 32个40位有符号数
);

	genvar gv_i;
    generate
        for (gv_i = 0; gv_i < 32; gv_i = gv_i + 1) begin
            mult_32_8 u_mult_32_8(
                .CLK(clk),
                .A(data1[gv_i*32 +: 32]),
                .B(data2[gv_i*8 +: 8]),
                .P(result[gv_i*40 +: 40])
            );
        end
    endgenerate
	
endmodule
